The present invention relates to an SOI substrate, and more particularly to improvements in insulation patterns provided on an interface between a pair of semiconductor substrates.
In recent years, the applications for multi-layered substrates bonded to each other such as silicon-on-insulator substrate (SOI substrate) have increased as bonding techniques have improved. The SOI substrate has an insulation buried layer such as a buried silicon oxide layer to act as a dielectric isolation substrate for high voltage devices such as power devices. For the power devices, it is required to increase the density of integration thereof, a high voltage and a high reliability. In these circumstances, a development of a new device so called "Intelligent Power Device" has recently been becoming active. In order to realize the intelligent power device, the silicon-on-insulator structure is partially and selectively formed in the substrate in order to integrate both a vertical power MOS field effect transistor circuit and a control circuit onto a single chip. This intelligent power device is, for example, disclosed in Japanese laid-open patent publication No. 4-29353.
FIG. 1 is a fragmentary cross sectional elevation view illustrative of a conventional intelligent power device wherein integration of control circuit regions 110 and a vertical power MOS field effect transistor circuit region 120 is shown. The SOI substrate has laminations of first and second monocrystal silicon substrates 100 and 200 bonded with each other. Silicon oxide patterns 101 are selectively provided on the control circuit regions 110 and on an interface between the first and second monocrystal silicon substrates 100 and 200. The silicon oxide film patterns 101 serve as the buried insulation film buried in the SOI substrate. Namely, in the control circuit regions 110, the first and second monocrystal silicon substrates 100 and 200 are indirectly bonded to each other through the silicon oxide film patterns 101. In the vertical power MOS field effect transistor circuit region 120, the first and second monocrystal silicon substrates 100 and 200 are directly bonded to each other. Control circuits are formed in the control circuit regions 110 whilst a vertical power MOS field effect transistor circuit is provided in the vertical power MOS field effect transistor circuit region 120. In the vertical power MOS field effect transistor circuit, a vertical power MOS field effect transistor has diffusion layers formed in a surface region of the first monocrystal silicon substrate 100. In the vertical power MOS field effect transistor circuit region 120, a drain electrode of the vertical power MOS field effect transistor is provided on a surface of the second monocrystal silicon substrate 200. The vertical power MOS field effect transistor flows a drain current from the diffusion layers toward the drain electrode through the interface between the first and second monocrystal silicon substrates 100 and 200. Namely, the interface between the first and second monocrystal silicon substrates 100 and 200 in the vertical power MOS field effect transistor circuit region 120 serves as a drain current path. This requires a physically and electrically perfect bonding between the first and second monocrystal silicon substrates 100 and 200 in the vertical power MOS field effect transistor circuit region 120.
In the plan view, the silicon oxide film patterns 101 are periodical based upon the individual chip size. FIG. 2 is a plan view illustrative of the conventional silicon oxide film patterns 101 of the above described SOI substrate shown in FIG. 1. The silicon oxide film patterns 101 comprise a plurality of parallel alignments of silicon oxide films rectangular-shaped in lateral direction, where the parallel alignments are separated from each other by the direct bonding regions 2, each of which is stripe-shaped to separate the adjacent two alignments of the rectangular-shaped silicon oxide films. The square area represented by broken lines correspond to the single chip area 1. The single rectangular-shaped silicon oxide film shears the bottom half part of the single chip area 1 whilst the directly bonding region shares the top half part of the single chip area 1. FIG. 1 is the cross sectional elevation view taken along I--I line in FIG. 2.
Electrical properties of the conventional power MOS field effect transistors were evaluated by the inventor of the present invention to confirm the facts that deterioration in the device properties is likely to appear depending upon the shapes of patterns of the silicon oxide films and the arrangements thereof. A bonding imperfection on the interface between the first and second monocrystal silicon substrates 100 and 200 was investigated. As a result, it was understood that a void representing the bonding imperfection or unbonded regions extends over a plurality of adjacent chip areas and the void causes the deterioration of the device performance. FIG. 3 is a plan view illustrative of the insulation patterns and voids on the interface between the first and second monocrystal silicon substrates 100 and 200 of the SOI substrate shown in FIG. 2. Each void is observed by ultrasonic examination. Each void is likely to extend in a direction parallel to the alignments of the silicon oxide film patterns 101. Namely, the deterioration of the device performance is likely to appear along the direction parallel to the alignments of the silicon oxide film patterns 101.
The above void may be caused by differences in flatness of and heat treatment to the first and second monocrystal silicon substrates 100 and 200 of the SOI substrate. Actually, however, it is difficult to bond the first and second monocrystal silicon substrates 100 and 200 without formation of any void on the interface between them. The directly bonding regions are inferior in bonding property than the indirectly bonding regions on which the silicon oxide film patterns 101 are provided on the interface between them. For this reason, the probability of formation of the void is higher in the directly bonding regions rather than the indirectly bonding regions on which the silicon oxide film patterns 101 are provided on the interface between them. Further, the formation of the voids is caused by a difference in level or a step between the silicon oxide film patterns and the monocrystal silicon substrate surface. Conditions for the formation of the silicon oxide films vary over positions of the substrate surface whereby some of the silicon oxide film patterns are higher in level than the monocrystal silicon substrate surface. In this case, the step or difference in level is formed between the silicon oxide film patterns and the monocrystal silicon substrate surface. For this reason, the indirect bonding between the first and second monocrystal silicon substrates 100 and 200 through the silicon oxide film pattern 101 is obtained prior to the direct bonding between the first and second monocrystal silicon substrates 100 and 200 without the silicon oxide film pattern 101. If the step or difference in level between the silicon oxide film patterns and the monocrystal silicon substrate surface is not so small, then the indirect bonding between the first and second monocrystal silicon substrates 100 and 200 through the silicon oxide film pattern 101 is obtained, whilst the direct bonding between the first and second monocrystal silicon substrates 100 and 200 without the silicon oxide film pattern 101 is difficult to obtain. Namely, the voids are likely to be formed in the direct bonding regions. Since the voids are caused by the difference in level between the silicon oxide film patterns and the monocrystal silicon substrate surface or difference in bonding conditions, the voids are likely to extend to the adjacent chip area. Allowance of such extensions of the voids to the adjacent chip area results in reduction in yield of the chips.
In the above circumstances, it had been required to develop a novel SOI substrate with improved insulator patterns free from the above problems.